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A Current-Feedback Instrumentation Amplifier With a Gain Error Reduction Loop and 0.06% Untrimmed
提出一种具有增益误差减少环的高精度电流反馈仪表放大器，适用于微弱信号处理。
0.7μm CMOS, 5V, 290μA, 0.06%增益误差, 5ppm INL
电流反馈仪表放大器增益误差动态元件匹配功率效率CMOS
▸创新点1：采用动态元件匹配（DEM）技术显著提高增益精度，通过动态切换输入和反馈跨导器的元件匹配，将未调整的最大增益误差降低至0.06%，同时改善增益漂移和线性度（方法创新）
▸创新点2：引入自动增益误差减少环（GERL）动态消除跨导器失配，无需传统 trimming 技术即可抑制 DEM 引起的输出纹波，实现 5-ppm INL 的高线性度（系统级创新）
▸创新点3：使用简单差分对结构替代电阻退化级设计，在保证增益精度的同时提升功率效率，功耗仅290μA@5V，噪声效率因子（NEF）达11.2（电路结构创新）
▸创新点4：整体架构实现127dB超高共模抑制比（CMRR）和3μV输入失调电压，适用于μV级传感器信号处理（性能指标突破）
Abstract
This paper presents a power-efficient current-feed- back instrumentation amplifier (CFIA) with high gain accuracy. It is intended for interfacing precision bridge transducers and thermocouples that output -level signals. The gain accuracy of the CFIA is mainly limited by the mismatch of two transcon- ductors. Applying dynamic element matching (DEM) to them ensures good gain accuracy, gain drift, and linearity. As a result, these transconductors can be implemented as simple differential pairs, resulting in significantly improved power efficiency when compared with the use of resistor-degenerated stages. To sup- press the output ripple caused by DEM, an automatic gain error reduction loop dynamically nulls the /109mismatch of the input and feedback transconductors, thus eliminating the need for trim- ming. The prototype chip was realized in a 0.7- m CMOS process. Measurement results show a maximum 0.06% untrimmed gain error and a 5-ppm INL at a gain of 100. This work also achieves an NEF of 11.2, a maximum input-referred offset of 3 V , and a CMRR of 127 dB while consuming only 290 A at a 5-V supply.