← 返回 JSSC 论文列表JSSC 2011第12期Clocking & PLLs0.13μmCDR
A TDC-Less 7 mW 25 Gbs Digital CDR With Linear Loop Dynamics and Offset-Free Dat
一种无TDC的7mW 25Gbs数字CDR，采用混合模拟/数字相位检测实现线性环路动态和零偏移数据恢复。
0.13μm CMOS, 1.2V, 2.5Gb/s时功耗7mW, 抖动5.7ps rms
数字时钟数据恢复电路混合模拟/数字相位检测抖动传输带宽线性环路动态无TDC设计
▸采用混合模拟/数字相位检测消除非线性与量化误差
▸实现与输入数据抖动无关的恒定抖动传输带宽
▸降低对数字控制振荡器频率量化误差和连续相同数字的敏感性
Abstract
E, Rajesh Inti , Student Member , IEEE, Amr Elshazly , Student Member , IEEE,
Mrunmay Talegaonkar, Student Member , IEEE , Brian Young , Student Member , IEEE , and
Pavan Kumar Hanumolu, Member , IEEE
Abstract—A digital clock and data recovery circuit (CDR) em-
ploys hybrid analog/digital phase detection to achieve linear loop
dynamics and to eliminate the nonlinearity and quantization error
of a bang-bang phase detector. The proposed architecture achieves
constant jitter transfer bandwidth inde