JSSC 2011第12期Data Converters40nmPipeline ADC

An 800 MSs Dual-Residue Pipeline ADC in 40 nm CMOS Davide V ecchi Jan Mulder Fra

40nm CMOS工艺下实现800 MS/s采样率的12位双残差流水线ADC，峰值SNDR达59dB。

40nm CMOS, 1V/2.5V双电源, 1.2V差分输入, 800MS/s, 59dB SNDR, 105mW

双残差流水线ADC背景校准交织采样高速ADC低功耗

▸双残差架构降低对残差放大器增益和带宽的敏感度

▸背景偏移校准技术提升ADC精度

▸四路交织技术实现高速采样

Abstract

This paper presents a 12-bit dual-residue pipeline ADC allowing the use of low gain and low bandwidth residue ampliﬁers to achieve 59 dB peak SNDR at 800 MSample/s. The dual-residue architecture is insensitive to the open-loop gain and the bandwidth of the residue ampliﬁers. However, their offset limits the accuracy of the entire ADC and therefore a background offset calibration technique was implemented. The high sampling speed was obtained through four times interleaving, requiring gain and of