An 8.5 mW Continuous-Time /1/6Modulator With 25 MHz Bandwidth Using Digital Background DAC Linearization to Achieve 63.5 dB SNDR and 81 dB SFDR John G. Kauffman, Student Member , IEEE

Abstract

This paper presents a third order, single-loop, contin- uous-time /1/6 modulator with an internal 4-bit quantizer. The modulator is sampled at 500 MHz, and features an oversampling ratio of only 10. Therefore, DAC linearization by dynamic element matching is ineffective, and the DAC nonlinearities are not cor- rected within the /1/6modulator loop but in the subsequent digital circuit. The unit element mismatches are digitally estimated based on a correlation, and correction factors are thus derived. Moreover, in order to achieve a low-power operation, all amplifiers are com- pensated for finite gain-bandwidth related non-idealities. In the presented work, this compensation includes the fast proportional loop, which is used to compensate for excess loop delay. The pre- sented /1/6 modulator has been realized in a 1.2 V , 90 nm CMOS process and achieves an SNDR of 63.5 dB and an SFDR of 81 dB within a 25 MHz bandwidth. The modulator occupies an active die area of only 0.15 mm /50and has a power consumption of 8 mW, with an additional 0.02 mm/50and 0.42 mW estimated for the digital DAC correction logic. The overall modulator achieves a figure of merit of 138 fJ/conv.