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Spur-Free Multirate All-Digital PLL for Mobile Phones in 65 nm CMOS
提出一种新型多速率全数字锁相环(ADPLL)架构，具备无杂散特性，适用于65纳米CMOS工艺的移动电话。
65nm CMOS, 1.2V, 32mA电流消耗, 0.35mm²面积
全数字锁相环多速率信号处理数字控制振荡器时间数字转换器无杂散
▸独立于参考频率的任意高数据速率调制能力
▸通过动态调整差分对失配和反馈时钟频率转换消除TDC量化噪声
▸采用低功耗技术如推测性时钟重定时和异步计数器
Abstract
enior Member , IEEE, Fikret Dülger , Member , IEEE,
and Oren E. Eliezer , Member , IEEE
Abstract—We propose a new multirate architecture of an all-dig-
ital PLL (ADPLL) featuring phase/frequency modulation capa-
bility. While the ADPLL approach has already proven its benefits
of power dissipation and cost reduction through the discrete-time
operation and full RF-SoC integration in nanoscale CMOS, the
coarse discretization of the phase detector function tends to keep it
from reaching the ultimate