← 返回 JSSC 论文列表
📄 下载 JSSC 原文 PDF
JSSC 2012第1期Other65nm

A 0013 mm505 22W DC-Coupled Neural Signal Acquisition IC With 05 V Supply

一种采用数字密集型架构的神经信号采集系统,通过双混合信号伺服环路实现0.5V供电下的高效面积利用。
65nm CMOS, 0.5V, 5μW, 4.9μVrms输入噪声
神经信号采集低功耗混合信号架构脑机接口医疗植入
数字密集型架构替代交流耦合电容和模拟滤波器
双混合信号伺服环路实现动作电位和局部场电位的同步数字化
噪声高效的DAC拓扑和紧凑的boxcar采样ADC
Abstract
ni , Member , IEEE, and Jan M. Rabaey , Fellow, IEEE Abstract—We present an area-efficient neural signal-acquisition system that uses a digitally intensive architecture to reduce system area and enable operation from a 0.5 V supply. The architecture replaces ac coupling capacitors and analog filters with a dual mixed-signal servo loop, which allows simultaneous digitization of the action and local field potentials. A noise-efficient DAC topology and an compact, boxcar sampling ADC are used to cancel