Abstract
Highly reliable and low power solid-state drive (SSD) is proposed. Through the analysis based on measured error rate in the SSDs with NAND flash memories, the memory cell error shows the asymmetric characteristic in multilevel cell (MLC) NAND flash memories. The proposed asymmetric coding increases the number of “1” s or “0” s of the programming data to reduce the data re- tention error. The numbers o f the memory cells in the higher states are reduced. The memory cell error is reduced by 90% with the asymmetric coding. On the other hand, the inter bit-line capac- itance significantly increases with the scaling of memory cells. The bit-line charging current becomes unacceptably large. To decrease the write power consumption, the stripe pattern elimination algo- rithm (SPEA) is proposed. The SPEA eliminates the column-stripe pattern which consumes the maximum power to charge all of the inter bit-line capacitance in a NAND chip. Theoretical analyses are given for both the a symmetric coding and the SPEA. The asym- metric coding and the SPEA can be used together with the other highly reliable or low power techniques such as intelligent inter- leaving and ada ptive code selection scheme and realizes the high reliability and low power consumption.