▸创新点1：非破坏性自参考感应技术NSRS（方法创新） - 通过利用MTJ高阻态和低阻态对单元电流幅度的不同依赖性，解决了传统感应技术在MTJ电阻位间差异大时的读取失败问题，实测显示可将读取失败率从10%降至0%。
▸创新点2：R-I曲线偏斜技术（电路创新） - 通过调整MTJ电阻-电流曲线的偏斜特性，优化了感应窗口，显著提升了感应裕量，确保最小感应裕量达到20mV。
▸创新点3：产量驱动的单元电流选择（系统创新） - 结合工艺变化特性动态选择最优单元工作电流，在保证读取可靠性的同时最大化芯片良率，支持15ns内完成完整感应过程。
▸创新点4：比率匹配技术（电路创新） - 通过精确匹配关键电路参数比率（如参考电阻与MTJ电阻的比率），进一步增强了NSRS方案的鲁棒性，使其在130nm工艺下实现12V/33V宽电压工作范围。
Abstract
Among all the emerging mem ories, Spin-Transfer Torque Random Access Memory (STT-RAM) has demonstrated many promising features such a s fast access speed, nonvolati lity, excellent scalability, and compatibility to CMOS process. However, the large process variations of b oth magnetic tunneling junction (MTJ) and MOS transistors in the scaled technologies seve rely limit the yield of STT-RAM chips. In this work, we proposed a new sensing scheme, named as nondestructive self-reference sensing, or NSRS, for STT-RAM. By leveraging the d ifferent dependencies of the high and low resistance states of MTJs on the cell current amplitude, the proposed NSRS technique can work well at the scenario when bit-to-bit variation of MTJ resistances is large. Furthermore, we proposed three combined magnetic- and circuit-level techniques, including R-I curve skewing, yield-driven cell current selection, and ratio matching, to further improve the sense margin and robustness of NSRS sensing scheme. The measurement results of a 16 Kb STT-RAM test chip show that our proposed nondestructive self-ref erence sensing technique can reliably readout all the measured memory bits, of which 10% read failure rate was observed by using the conventional sensing technique. The three enhanc ement technologies ensure a 20 mV minimum sense margin and the whole sensing process can complete within 15 ns.