JSSC 2012第2期Memory65nmDRAM

A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell fo

提出了一种667 MHz逻辑兼容嵌入式DRAM，采用非对称2T增益单元和电流模式感放技术，显著提升读写速度和能效。

667 MHz随机周期频率，1.65 ns延迟，1.1 V电压，85°C温度

嵌入式DRAM非对称2T增益单元电流模式感放器半摆幅写入65nm CMOS

▸非对称2T增益单元利用PMOS写入器件的漏电流维持高电平

▸电流模式感放器（C-S/A）改善电压裕度和阻抗匹配

▸半摆幅写入位线（WBL）方案提升写入速度33%并降低功耗25%

Abstract

Circuit techniques for enhancing the rete ntion time and random cycle of logic-compatible embedded DRAMs (eDRAMs) are presented. An asymmetric 2T gain cell utilizes the gate and junction leakages of a PMOS write device to main- tain a high data ‘1’ voltage level which enables fast read access using an NMOS read device. A current-mode sense ampli ﬁer (C-S/A) featuring a cross-coupled PMOS la tch and pseudo-PMOS diode pairs is proposed to overcome the innate problem of small read bit-line (RBL) vo