A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches Ki Chul Chun, Pulkit Jain, Tae-Ho Kim, and Chris H. Kim , Senior Member , IEEE

Abstract

Circuit techniques for enhancing the rete ntion time and random cycle of logic-compatible embedded DRAMs (eDRAMs) are presented. An asymmetric 2T gain cell utilizes the gate and junction leakages of a PMOS write device to main- tain a high data ‘1’ voltage level which enables fast read access using an NMOS read device. A current-mode sense ampli fier (C-S/A) featuring a cross-coupled PMOS la tch and pseudo-PMOS diode pairs is proposed to overcome the innate problem of small read bit-line (RBL) voltage swing in 2T eDRAMs with im- proved voltage headroom and better impedance matching under process–voltage–temperature (P VT) variations. A half-swing write bit-line (WBL) scheme is adopted to improve the WBL speed by 33% and reduce its power d issipation by 25% during write-back operation with no effect on retention time. A stepped write word-line (WWL) driver reduces the current drawn from the boosted high and low suppli es by 67%. A 192 kb eDRAM test chip with 512 cells-per-BL implemented in a 65 nm low-power (LP) CMOS process shows a random cycle frequency and latency of 667 MHz and 1.65 ns, resp ectively, at 1.1 V and 85 C. The measured refresh period at a 99.9% bit yield condition was 110 s which is comparable to that of recently published 1T1C eDRAM designs.