An Embedded DRAM Technology for High-Performance NAND

Abstract

An embedded DRAM using a standard NAND flash memory process has been demonstrated for the first time. This embedded DRAM without extra costly manufacturing process realizes 2.4 mm /Mb macro density and provides large-capacity on-chip page buffers and data caches for NAND flash memories to enhance their performa nces. A 32 KB DRAM buffer macro with 1.5 m cell has been fabricated with a 32 nm NAND flash memory process. Even with small 3 fF cell using a planar MOS capacitor, an enough 100 mV cell signal has been obtained by introducing a technique to self-boost cell node up to 4 V using a merit of high-voltage NAND flash process, and two techniques to curtail parasitic bitline capacitance down to 60 fF a t 128 wordlines per bitline. An unders hoot problem of cell nodes due to unwanted plateline bounce is resolved by a two-step-rise/fall wordline scheme. Installation of dummy cell scheme t oo b t a i na half of “1” data (not an average of “1” and “0” data) cuts out 32 KB macro size by 1.3% while suppressing mismatch to 3 mV at the grounded bitline precharge. The 32 KB test ve hicle shows 90 ns random cycle time with 15 ns burst cycle time (66 Mb/s/pin). The measured characteristics of 2 10 bit error rater (BER) by soft error and 10 ms data retention at 85 C are enough for page buffer application in a NAND flash memory. The measured active current of 32 KB macro is 7 mA at 90 ns random cycle, but only 3.2 mA at practical use of 15 ns burst with 256B page access.