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An Embedded DRAM Technology for High-Performance NAND Flash Memories Daisaburo T
首次展示了一种用于高性能NAND闪存的嵌入式DRAM技术，无需额外制造工艺。
32KB DRAM缓冲宏，1.5μm单元，90ns随机周期时间，15ns突发周期时间（66Mb/s/pin）
嵌入式DRAMNAND闪存高电压工艺单元信号提升字线方案
▸使用标准NAND闪存工艺实现嵌入式DRAM
▸采用自升压技术提升单元信号至4V
▸通过两步升降字线方案解决单元节点下冲问题
Abstract
An embedded DRAM using a standard NAND flash
memory process has been demonstrated for the first time. This
embedded DRAM without extra costly manufacturing process
realizes 2.4 mm /Mb macro density and provides large-capacity
on-chip page buffers and data caches for NAND flash memories
to enhance their performa nces. A 32 KB DRAM buffer macro
with 1.5 m cell has been fabricated with a 32 nm NAND flash
memory process. Even with small 3 fF cell using a planar MOS
capacitor, an enough
100 mV cell signa