← 返回 JSSC 论文列表JSSC 2012第3期Digital Circuits0.13μm CMOSNeural Network Accelerator
A 0.5-V 35- W 85-dB DR Double-Sampled Modulator for
提出一种0.5V供电、35.2μW功耗的音频双采样调制器,采用输入前馈拓扑降低信号摆幅,通过补偿环路保持噪声传递函数稳定性。
0.5V供电, 35.2μW功耗, 81.7dB SNDR, 82.4dB SNR, 85.0dB DR, 20kHz带宽
低电压双采样调制器音频应用噪声传递函数功耗优化
▸输入前馈拓扑降低内部信号摆幅
▸补偿环路保持噪声传递函数稳定性
▸基于电阻串参考开关矩阵的直接求和量化器简化模拟补偿环路
Abstract
This paper presents a 0.5-V 1.5-bit double-sam- pled modulator for audio applications. Unlike existing double-sampled designs, the proposed double-sampled mod- ulator employs an input-feedforward topology to reduce internal signal swings, thereby relaxing design requirements for the low-voltage building blocks and re ducing distortion. Moreover, in order to avoid instability and noise shaping degradation, the proposed architecture restores th e noise transfer function (NTF) of the double-sampled modulator to its single-sampled equivalent with the help of compensation loop s. In the circuit implementa- tion, the proposed fully-differential ampli fier adopts an invert er output stage and a common-mode feedback (CMFB) circuit with a global feedback loop in order to reduce power consumption. A resistor-string-reference switch matrix based on a dire ct summa- tion quantizer is used to simplify the analog compensation loop. The chip prototype has been fabricated in a 0.13- CMOS t e c h n o l o g yw i t hac o r ea r e ao f0 . 5 7m m.T h em e a s u r e dr e s u l ts show that when operating from a 0.5-V supply and clocked at 1.25 MHz, the modulator achiev es a peak signal-to-noise and distortion ratio (SNDR) of 81.7 dB, a peak signal-to- noise ratio (SNR) of 82.4 dB and a dynamic range (DR) of 85.0 dB while consuming 35.2 W for a 20-kHz signal bandwidth.