A 1.9–3.8 GHz Fractional-N PLL Frequency Synthesizer With Fast Auto-Calibration of Loop Bandwidth and VCO Frequency

Abstract

A fast and high-precision all-digital aut omatic calibration circuit that is highly suited for fractional-N synthesizers is designed to achieve a constant loop bandwidth and fast lock time over an octave tuning range . A high-speed frequency-to-digital converter (FDC) measures VCO frequency o n - c h i pw i t has u b - frequency resolution of in a time period of . The on-chip detected VC O frequency is then used for calibrating the loop bandwidth and the VCO frequency. The loop bandwidth calibration circuit measures the VCO gain and uses it to precisely co ntrol the charge pump current, hence making the loop bandwidth constant. For the VCO frequency calibration, a minimum error code finding block significantly enhances the calibration accuracy by finding the truly closest code to the target frequency. Moreover, this method does not need to activate modulator to achieve sub- calibra- tion resolution, which makes t his technique much accurate and faster than the conventional ones. A 1.9–3.8 GHz fractional-N synthesizer is implemented in 0.13 m CMOS, demonstrating that the loop bandwidth calibr ation is completed in 1.1–6.0 sw i t h % accuracy and the VCO frequenc y calibration is completed in 1.225–4.025 s, all across the entire octave tuning range.