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A 40-Gbs Optical Transceiver Front-End in 45 nm SOI CMOS Joohwa Kim Member IEEE
45nm SOI CMOS工艺下实现低功耗40Gb/s光收发器前端
45nm SOI CMOS, 1V, 40Gb/s, 9mW, 1875 Ω/pJ
光收发器SOI CMOS低功耗TIA40Gb/s
▸创新点1：采用浮体晶体管技术实现单端和差分光调制器，通过优化器件结构实现2V和4V的输出摆幅，显著提升调制效率（方法创新）
▸创新点2：设计高增益宽带前端，在33GHz带宽内实现7.6dB单端增益，突破传统CMOS工艺的频率限制（电路创新）
▸创新点3：开发超低功耗TIA架构，在1V供电下仅消耗9mW，达到1875Ω/pJ的优值系数，创下40Gb/s CMOS接收机的最低功耗记录（系统创新）
▸创新点4：通过创新的群延迟补偿技术，在30GHz带宽内将群延迟变化控制在3.9ps以内，显著改善信号完整性（电路创新）
Abstract
A low-power, 40-Gb/s opti cal transceiver front-end
is demonstrated in a 45-nm silicon-on-insulator (SOI) CMOS
process. Both single-ended and d ifferential optical modula-
tors are demonstrated with floating-body transistors to reach
output swings of more than 2
and 4 , respectively.
A single-ended gain of 7.6 dB is measured over 33 GHz. The
optical receiver consists of a transimpedance ampli fier (TIA) and
post-amplifier with 55 dB of transimpedance over 30 GHz. The
group-delay variation is 3.9 ps