Power and Area Minimization of Recon figurable FFT Processors A 3GPP-LTE Example

Abstract

This paper presents a desi gn methodology for power and area minimization of flexible FFT processors. The method- ology is based on the power-area tradeoff space obtained by adjusting algorithm, architect ure, and circuit variables. Radix factorization is the main techni que for achieving high energy efficiency with flexibility, followed by architecture parallelism and delay line circuits. The flexibility is provided by recon fig- urable processing units that support radix-2/4/8/16 factorizations. As