Synchronous-Logic and Globally-Asynchronous- Locally-Synchronous (GALS) Acoustic Digital

Abstract

We design an Acoustic Digital Signal Processor (ADSP) SoC, the primary signal processing module of an acoustic signal detection syste m, based on two design approaches: fully-synchronous (Fully-Sync), a nd globally-asynchronous-lo- cally-synchronous (GALS). The emphasis of the ADSP designs is low power operation where both designs embody modular-level and circuit-level clock gating techniques. For sake of fair bench- marking, both ADSPs have identical functionality, are designed using the same 130 nm CMOS proc ess, and largely embody the same library cells (save that for the signaling protocols in the GALS ADSP). The GALS ADSP is substantially more power-ef- ficient (the Fully-Sync ADSP dissipates more power @ nominal V) and the only cost is the marginally higher IC area. Its higher power ef ficiency is largely attributed to the exploitation of asynchronous signaling between circuit modules by means of more finely-grained partitioning of the clock domains; intra-circuit signaling therein remains fully-sync. This provides for the ensuing simpli fication of the clocking in- frastructure and subse quent reduction of the global clock rate. The prototype GALS ADSP is able to operate to speci fications throughout the lifespan of the battery ( V–1.4 V , in part depicting Dynamic Voltage Scaling attributes) and at V , it dissipates 186 W.