← 返回 JSSC 论文列表JSSC 2012第4期Data Converters40nmPipeline ADC
A 12-Bit 3 GSs Pipeline ADC With 04 mm and 500 mW in 40 nm Digital CMOS Chun-Yin
提出一种12位3GS/s的40纳米CMOS流水线ADC，采用自适应电源/地架构和参考外推方案，实现高性能。
12位分辨率，3GS/s采样率，61dB SNR，0.5LSB DNL，500mW功耗
ADC流水线时间交织CMOS高采样率
▸自适应电源/地架构消除纳米级CMOS电源限制
▸参考外推方案优化信号摆幅
▸双路时间交织设计提升采样率
Abstract
A 12-bit 3 GS/s 40 nm two-way time-interleaved
pipeline analog-to-digital conv erter (ADC) is presented. The
proposed adaptive power/ground architecture eliminates the
headroom limitations due to the deeply scaled power supply in
nanometer CMOS technologies, while preserving the intrinsic
speed of thin-oxide MOSFETs w ith minimum channel length
for key analog blocks. Moreover , in terms of the signal swing,
the proposed reference extrapolation scheme offers a smooth
transition between the multip