A 12-Bit 3 GS/s Pipeline ADC With 0.4 mm and 500 mW in 40 nm Digital CMOS Chun-Ying Chen, Jiangfeng Wu, Juo-Jung Hung, Tianwei Li

Abstract

A 12-bit 3 GS/s 40 nm two-way time-interleaved pipeline analog-to-digital conv erter (ADC) is presented. The proposed adaptive power/ground architecture eliminates the headroom limitations due to the deeply scaled power supply in nanometer CMOS technologies, while preserving the intrinsic speed of thin-oxide MOSFETs w ith minimum channel length for key analog blocks. Moreover , in terms of the signal swing, the proposed reference extrapolation scheme offers a smooth transition between the multiply ing digital-to-analog converter stages and the last flash stage. With these two techniques, the ADC achieves a SNR of 61 dB and a DNL of 0.5 0.5 LSB, while consuming 500 mW at a 3 GS/s sampling rate and occupying an area of 0.4 mm in 40 nm CMOS process.