A 12.8-Gb/s/link Tri-Modal Single-Ended

Abstract

This paper presents a tri-modal asymmetric memory controller interface that achiev es 12.8-Gbps single-ended (SE) signaling over stripline FR4 traces. The controller can be con- figured to communicate with commercially available GDDR5 and DDR3 memories at 6.4 and 1.6 Gbps, respectively, with no package change. The interface is equippe d with a compact voltage-mode driver with 1-tap pre-emphasis, in the WRITE direction, and a linear equalizer (LEQ) and 1 - t a pd e c i s i o nf e e d b a c ke q u a l - izer (DFE), in the READ direction, to compensate for channel inter-symbol interference (ISI). The receiver front-end contains a supply noise tracking scheme to mitigate reference voltage (VREF) noise. A tri-VCO PLL and an ef ficient global clock distri bution scheme support a wide range of o perating frequencies at low power consumption. Finally, the interface also incorporates two overhead links per byte for data-bus encoding (DBE) e xperiments to mitigate simultaneous switching noise (SSN). Implemented in a 40-nm CMOS process, the 16 tri-modal interface achieves an energy ef ficiency of better than 5.0 mW/Gbps pe r data link at 12.8 Gbps.