← 返回 JSSC 论文列表JSSC 2012第4期Wireline I/O40nmDRAM
A 128-Gbslink Tri-Modal Single-Ended Memory Interface Amir Amirkhany Member IEE
一款支持三模式、12.8Gbps单端信号传输的内存接口控制器
12.8 Gbps, 5.0 mW/Gbps
内存接口单端信号GDDR5DDR3CMOS
▸创新点1：三模式不对称内存控制器，支持12.8 Gbps单端信号传输，兼容GDDR5和DDR3内存，无需更改封装，显著提升系统灵活性。
▸创新点2：紧凑型电压模式驱动器，配备1-tap预加重技术，有效减少写入方向的符号间干扰，提升信号完整性。
▸创新点3：供应噪声跟踪方案，通过跟踪电源噪声，减少参考电压噪声，提高接收器前端抗干扰能力。
▸创新点4：全局时钟分布方案，结合三VCO PLL，支持宽频操作，降低功耗，实现高效时钟管理。
Abstract
This paper presents a tri-modal asymmetric memory
controller interface that achiev es 12.8-Gbps single-ended (SE)
signaling over stripline FR4 traces. The controller can be con-
figured to communicate with commercially available GDDR5 and
DDR3 memories at 6.4 and 1.6 Gbps, respectively, with no package
change. The interface is equippe d with a compact voltage-mode
driver with 1-tap pre-emphasis, in the WRITE direction, and
a linear equalizer (LEQ) and 1 - t a pd e c i s i o nf e e d b a c ke q u