A 2.37-Gb/s 284.8 mW Rate-Compatible (491,3,6) LDPC-CC Decoder Chih-Lung Chen, Y u-Hsiang Lin, Hsie-Chia Chang

Abstract

This paper presents a (491,3,6) time-varyin gl o w - d e n - sity parity check convolutional code (LDPC-CC) decoder chip. This work combines the algorithm level, node level, and bit level optimizations to achieve over 2 Gb/s throughpu t with acceptable hardware cost and power. The algorithm level optimization is the on-demand variable node activat ion scheduling with concealing channel values, which can not only achieve t wice faster decoding convergence speed than log-belief p ropagation (log-BP) algorithm, but also reduce the 17% message st orage capacity. The node level optimization duplicates the check node u nits and variable node units and unfolds the message storage first-in–first-outs (FIFOs) so that the throughput becomes twelve multiplying with clock frequency. In the meantime, the bit level optimization is employed to retime the critical path such that the higher clock frequency can be achieved and message storage size is slightly reduced. Furthermore, a novel hybrid-par titioned FIFO is proposed to provide suf ficient memory bandwidth to processing units and alleviate power consumption. With these schemes, a test chip of proposed LDPC-CC decoder has b een fabricated in 90 nm CMOS technology with core area of . Maximum throughput 2.37 Gb/s is measured under 1.2 V supply with energy efficiency of 0.024 nJ/bit /proc. Depending on the operation mode, power can be scaled down to 90.2 mW while maintaining 1.58 Gb/s at 0.8 V supply.