A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS Thomas Toifl, Senior Member , IEEE, Christian Menol fi, Member , IEEE

Abstract

A low-power receiver circuit in 32 nm SOI CMOS is p r e s e n t e d ,w h i c hi si n t e n d e dt ob eu s e di nas o u r c e - s y n c h r o n o u s link con figuration. The design of the receiver was optimized for power owing to the assumption that a link protocol enables a periodic calibration during which the circuit does not have to deliver valid data. In addition, it is shown that the transceiver power and the effect of high-freq uency transmit jitter can be reduced by implementing a linear equalizer only on the receive side and avoiding a transmit feed-forward equalizer (TX-FFE). On the circuit level, the receive r uses a switched-capacitor (SC) approach for the implementatio no fa n8 - t a pd e c i s i o n - f e e d b a c k equalizer (DFE). The SC-DFE improves the timing margin rel- ative to previous DFE implementations with current feedback, and leads to a digital-style circuit implementation with compact layout. The receiver was measured at data rates up to 13.5 Gb/s, where error free operation was veri fied with a PRBS-31 sequence and a channel with 32 dB attenuation at Nyquist. With the clock generation circuits amortized ove r eight lanes, the receiver circuit consumes 2.6 mW/Gbps from a 1.1 V supply while running at 12.5 Gb/s.