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A 26 mWGbps 125 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS Thomas T
32nm SOI CMOS工艺下的低功耗接收器电路，采用8抽头开关电容DFE，支持12.5 Gbps数据传输。
32nm CMOS, 1.1V, 12.5 Gb/s, 2.6 mW/Gbps
低功耗接收器开关电容DFESOI CMOS源同步链路线性均衡器
▸采用开关电容(SC)技术实现8抽头判决反馈均衡器(DFE)
▸仅在接收端实现线性均衡器，避免使用发射前馈均衡器(TX-FFE)
▸数字式电路实现，布局紧凑
Abstract
A low-power receiver circuit in 32 nm SOI CMOS is
p r e s e n t e d ,w h i c hi si n t e n d e dt ob eu s e di nas o u r c e - s y n c h r o n o u s
link con figuration. The design of the receiver was optimized for
power owing to the assumption that a link protocol enables a
periodic calibration during which the circuit does not have to
deliver valid data. In addition, it is shown that the transceiver
power and the effect of high-freq uency transmit jitter can be
reduced by implementing a linear