JSSC 2012第4期Other40nm

A 27 Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive V oltage Scali

提出了一种采用通用延迟线（UDL）的自适应电压调节技术，用于降低40纳米CMOS多媒体SoC的功耗。

40-nm CMOS, 27% active power reduction

自适应电压调节通用延迟线功耗降低多媒体SoCCMOS

▸使用通用延迟线（UDL）替代传统的复制延迟线

▸分布式4个监测器以减少芯片内变异误差

▸简化监测器设计同时保持低误差

Abstract

A VS technique for extremely scaled SoCs has been developed. T o reduce design cost, we have developed a supply voltage control scheme employing universal delay line (UDL), rather than a replica delay line, for monitoring the critical path delay . The UDL can be used in any product without any need for customizing. In addi tion, averaging the results of distributed 4 monitors with a pitch of 3 mm in a chip can reduce errors due to within-die variation by half. With these techniques, proposed sch