A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive V oltage Scaling Using Distributed Universal Delay Lines Y oshifumi Ikenaga

Abstract

A VS technique for extremely scaled SoCs has been developed. T o reduce design cost, we have developed a supply voltage control scheme employing universal delay line (UDL), rather than a replica delay line, for monitoring the critical path delay . The UDL can be used in any product without any need for customizing. In addi tion, averaging the results of distributed 4 monitors with a pitch of 3 mm in a chip can reduce errors due to within-die variation by half. With these techniques, proposed scheme produces equivalent or less error to than does a conventional scheme that uses a single critical path replica as a delay monitor, even with simple monitor design. We have shown that 40-nm CMOS SoCs using our A VS can reduce active power by 27%.