An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects Timothy O. Dickson , Member , IEEE,Y o n g L i u, Member , IEEE, Sergey V . Rylov , Member , IEEE

Abstract

A source synchronous I/O system based on high-den- sity silicon carrier interconnects is introduced. Bene fiting from the advantages of advanced silicon pa ckaging technologies, the system uses 50 m-pitch C4s to reduce I/O cell size and fine-pitch interconnects on silicon carrie r to achieve record-breaking in- terconnect density. An I/O architecture is introduced with link redundancy such that any link can be taken out of service for periodic recalibration without in terrupting data transmission. A timing recovery system using two phase rotators shared across all bits in a receive bus is presented. To demonstrate these concepts, an I/O chipset using this architecture is fabricated in 45 nm SOI CMOS technology. It includes co mpact DFE-IIR equalization in the receiver, as well as a new all-CMOS phase rotator. The chipset is mounted to a silicon c a r r i e rt i l ev i aP b - f r e eS n A g C4 solder bumps. Chip-to-chip communication is achieved over ultra-dense interconnects with pitches of between 8 ma n d2 2 m. 8 10-Gb/s data is received over distances up to 4 cm with al i n ke n e r g ye fficiency of 5.3 pJ/bit from 1 V TX and RX power supplies. 8 9-Gb/s data is recovered from a 6-cm link with 16.3 dB loss at 4.5 GHz with an ef ficiency of 6.1 pJ/bit.