Compact Measurement Schemes for Bit-Line Swing Sense Amplifier Offset V oltage an

Abstract

This paper proposes schemes for the direct measure- ment of bit-line (BL) voltage swing, sense ampli fier (SA) offset voltage, and word-line (WL) pul se width, demonstrated in a 40 nm CMOS 32 kb fully functional SRAM macro with 2% area penalty. This is the first such scheme to enable the optimal tuning of WL-pulse (WLP) width accord i n gt oo n - s i t em e a s u r e m e n t results for BL voltage swing, dynamic read stability, and write margin, all of which depend on WLP width. It also eliminates