Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset V oltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM Y en-Huei Chen, Shao-Y u Chou, Quincy Li, Wei-Min Chan, Dar Sun, Hung-Jen Liao, Ping Wang, Meng-Fan Chang, and Hiroyuki Y amauchi

Abstract

This paper proposes schemes for the direct measure- ment of bit-line (BL) voltage swing, sense ampli fier (SA) offset voltage, and word-line (WL) pul se width, demonstrated in a 40 nm CMOS 32 kb fully functional SRAM macro with 2% area penalty. This is the first such scheme to enable the optimal tuning of WL-pulse (WLP) width accord i n gt oo n - s i t em e a s u r e m e n t results for BL voltage swing, dynamic read stability, and write margin, all of which depend on WLP width. It also eliminates the need for additional margins related to BL voltage swing, which has conventionally been required to ensure adequate tolerances against simulation errors and inaccurate estimation of SA offset voltage. This opens up possibilities for a more aggressive approach to deal with WLP width instead of only ensuring the target BL voltage swing.