Isolation Techniques Against Substrate Noise Coupling Utilizing Through Silicon Via (TSV) Process for RF/Mixed-Signal SoCs

Abstract

The isolation techniques against substrate noise cou- pling utilizing through silicon via (TSV) process are described. The trench shape TSV encloses the RF circuit on a SoC chip to improve the isolation between digital circuits and the RF circuits without constraints of on-chip interconnect above first metal as the TSV is connected to the grounded 1st metal from the back side of the sub- strate. The analysis with simpli fied model is proposed to show the effect of the proposed isolation techniques. Mesh circuit model is applied to simulate the noise distribution in detail. Various test pat- terns are fabricated on a CMOS sil icon substrate with resistivity of 10 . The measurement pattern of H-shaped TSV con firms about 30 dB and 40 dB improvement at 100 MHz and 1 GHz re- spectively, which is much better tha n conventional isolation tech- niques such as guard ring, Deep N-well and DTI. The combina- tional pattern with TSV , DTI and high resistive layer shows 60 dB improvement of the isolation. Pro posed isolation techniques are useful for substrate noise coupling of future RF/mixed-signal SoCs.