A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS

Abstract

This paper presents a 10-bit 80-MS/s successive ap- proximation time-to-digital converter (TDC) with a decision-select structure for on-chip timing measu rement applications. Time-do- main successive approximation is realized utilizing a relative timing difference between input a nd reference timings. While the successive approximation scheme allows high bit resolutions and low power consumptions, the decision-select structure enables fast bit conversions that lead to high sampling rates. The decision-se- lect structure unrolls the success ive approximation iteration loop and removes time-consuming tim ing estimation and adjustment procedures to minimize bit conversion times. As the successive approximation scheme relies on a bi nary search, exponential delay lines are adopted to achieve good power and noise performances by reducing the total number of delay stages. The proposed TDC uses only 0.048 delay stages per bi t conversion. A test-chip proto- type fabricated in a 65-nm CMOS technology consumes 9.6 mW at 80-MS/s and demonstrates 0.23-pJ/conversion-step figure-of merit (FOM) and 0.5-LSB single-shot precision.