← 返回 JSSC 论文列表JSSC 2012第5期Data Converters0.13μmDAC
A 35 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modula
提出一种基于无记忆牛顿-拉夫森调制曲线的35GHz扩频时钟发生器，采用FLL结构实现多频偏支持与EMI抑制。
0.13μm CMOS, 3.5GHz, 23.72mW, 0.076mm², EMI抑制19.14dB
扩频时钟发生器牛顿-拉夫森算法频率锁定环EMI抑制MASH调制器
▸采用无记忆牛顿-拉夫森算法生成非线性调制曲线
▸双二进制加权DAC结合1-1-1 MASH调制器
▸支持14种频偏(0.5%~3.5%)和3种调制频率
Abstract
A frequency-locked loop (FLL) based spread-s pec-
trum clock generator (SSCG) with a memoryless Newton-Raphson
modulation pro file is introduced in this paper. The SSCG uses
an FLL as a main clock generator. It brings not onl ya na r e a
reduction to the SSCG but also the advantage of having multiple
frequency deviations. A double b inary-weighted DAC is proposed
that modulates the frequency information of the frequency de-
tector using a 1-1-1 MASH
modulator. The Newton-Raphson
mathematical algo