← 返回 JSSC 论文列表JSSC 2012第5期Clocking & PLLs0.13 µm
A 56 GHz to 115 GHz DCO for Digital Dual Loop CDRs
实现了一个56 GHz至115 GHz的数字控制振荡器，用于数字双环CDR电路。
0.13 µm CMOS, 1.2 V, 299 fs @ 9.953 Gb/s
数字控制振荡器CMOS温度变化正交输出CDR
▸在0.13 µm CMOS工艺中实现
▸支持超过130°C的温度变化跟踪
▸产生2.8 GHz至5.8 GHz的正交输出
Abstract
A DCO is realized in 0.13 mC M O Su s i n g4c o r e sf o r
a 5.6 to 11.5 GHz octave tuning bandwidth to provide the clock for
an all digital D/PLL CDR circuit. The DCO is novel in that it can
track more than a 130 degree C temperature variation while the
CDR maintains an error free lock to data. Each core is directly cou-
pled to a div/2 to produce I/Q signals that a 4:1 MUX combines into
a single set of 2.8 to 5.8 GHz quadrature outputs to drive the sine
interpolator of the CDR. Locked to maxim