JSSC 2012第6期Data Converters90nmPipeline ADCDAC

A 10-b 320-MSs Stage-Gain-Error Self-Calibration Pipeline ADC Chien-Jian Tseng S

提出一种采用低增益运放和自校准技术的10位320MS/s流水线ADC

90nm CMOS, 320MS/s, SFDR 66.7dB, SNDR 54.2dB, 42mW, 0.21mm²

流水线ADC自校准低增益运放电容阵列高速转换

▸低直流增益运放（30.6dB）设计

▸基于电容阵列的级间增益误差自校准技术

▸无外部精密参考源的校准方案

Abstract

A 10-b 320-MS/s pipeline analog-to-digital converter (ADC) with low dc gain opamps, as low as 30.6 dB based on simu- lations, in its multiplying digital-to-analog converters (MDACs) is presented. A foreground self-calibration technique is proposed to reduce stage gain error by adjusting feedback factor with a calibra- tion capacitor array. The prototype in 90-nm low-power CMOS technology achieves conversion rate of 320 MS/s with peak SFDR and SNDR of 66.7 and 54.2 dB, respectively. The total pow