JSSC 2012第6期Clocking & PLLs5nm/4nmDLL

A 10-ns10-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Control

提出一种具有竞速模式和计数器CAS延迟控制的10ns10V延迟锁定环(DLL)，实现低功耗、低抖动和快速锁定。

1.5ns tCK下512周期内将10%占空比误差校正至2%以内，1.2V下工作频率超过1.0GHz

延迟锁定环DDR3 SDRAM低功耗低抖动CAS延迟控制

▸采用竞速模式的双DLL架构

▸合并双粗延迟线(MDCDL)降低功耗

▸OR-AND功能占空比校正器(OR-AND DCC)

Abstract

The digital delay-locked loop (DLL) with racing mode and the countered column address strobe (CAS) latency controller are proposed in this paper. The dual-DLL architecture with racing operation is adopted to achieve low power consump- tion, low jitter, fast locking, wide range of locking, and stuck-free control. The merged dual coarse delay line (MDCDL) reduces the dynamic power consumption of a variable delay line by 30% by sharing a part of the delay line path in DLL. In addition, jitter is re