A 1500 fps Highly Sensitive 256 256 CMOS Imaging Sensor With In-Pixel Calibration Ruoyu Xu, Student Member , IEEE, Bing Liu , Student Member , IEEE, and Jie Y uan, Member , IEEE

Abstract

High-speed CMOS imaging sensors (CIS) norma lly have low sensitivity because of the large integration capacitance. They also have high noise because pixel circuits cannot imple- ment correlated double sampling (CDS) to remov e the pixel reset noise. For applications, such as micro-computed tomography (micro-CT), this is a major limitation. In this work, we devel- oped a technique to achieve high sensitivit ya n dl o wn o i s ef o r high-speed CIS. To maximize the sensitivity, we designed a new capacitive transimpedance ampli fier (CTIA) pixel with a tiny metal–oxide–metal capacitor. The pixel circuit also implements CDS. As a result, the temporal noise is greatly reduced, and the sensitivity improves dramatically. To compensate the mismatch of small integration capacitors ac ross the pixel array, an on-chip calibration scheme with in-pixel circuits is developed. Fully differ- ential column circuits are designed to suppress the power supply injection in the large array of hi gh-speed column circuits. A suc- cessive-approximation analog-to-digital (SAR ADC) is designed to achieve 10-bit resolution and to fit in the 15- mc o l u m np i t c h . For testing modes, column circ uits are con figured into a two-step ADC to provide 13-bit dynamic range. The 256 256 CIS design is fabricated in a 0.18- m CMOS process. The imager samples up to 1500 fps. The pixel in tegration capacitor is 0.7 fF, which enables 68.5 V/lux s sensitivity under the white illumination. The CIS temporal noise is .