← 返回 JSSC 论文列表JSSC 2012第7期Clocking & PLLsNeural Network Accelerator
A 126 Gbs 42 pJBit Clock Data Recovery Circuit With High Jitter Tolerance in 01
提出一种高并行时钟数据恢复电路，具有高抖动容限和低功耗特性。
126 Gb/s, 42 pJ/bit, 4.3 Unit Interval抖动容限@1MHz
时钟数据恢复高并行低功耗抖动容限CMOS逻辑
▸输入直接解复用降低电路速度要求
▸标准CMOS逻辑广泛使用实现低功耗
▸位速率相位反馈提高抖动容限
Abstract
In this paper, a highly parallelized Clock & Data Re-
covery (CDR) circuit with phase feedback at the bit rate is pre-
sented. This parallel CDR features demultiplexing directly at the
input, which reduces circuit speed requirements and enables ex-
tensive use of standard CMOS logic which only draws dynamic
power, resulting in excellent power ef ficiency over a wide range of
speeds: an almost constant 4.2 pJ /bit between 2.4 and 6 Gb/s. Par-
allel CDRs traditionally have limited loop bandwidth an