A 1.2–6 Gb/s, 4.2 pJ/Bit Clock & Data Recovery Circuit With High Jitter Tolerance in 0.14 mC M O S Arnoud P . van

Abstract

In this paper, a highly parallelized Clock & Data Re- covery (CDR) circuit with phase feedback at the bit rate is pre- sented. This parallel CDR features demultiplexing directly at the input, which reduces circuit speed requirements and enables ex- tensive use of standard CMOS logic which only draws dynamic power, resulting in excellent power ef ficiency over a wide range of speeds: an almost constant 4.2 pJ /bit between 2.4 and 6 Gb/s. Par- allel CDRs traditionally have limited loop bandwidth and jitter tol- erance due to latency in the phase-feedback loop. Our architecture solves this problem by applying feedback at the bit rate, resulting in jitter tolerance beyond 4.3 Unit Interval at 1 MHz.