← 返回 JSSC 论文列表JSSC 2012第7期Power Management90nmVCOTDC
A 36 mW 90 nm CMOS Gated-V ernier Time-to-Digital Converter With an Equivalent R
一种采用门控环形振荡器的改进型Vernier时间数字转换器，进一步降低了量化噪声。
90nm CMOS, 1.2V, 25MHz, 3mA, 5.8ps分辨率, 3.2ps等效噪声分辨率
时间数字转换器门控环形振荡器Vernier结构量化噪声CMOS
▸采用门控环形振荡器（GRO）作为延迟线
▸进一步降低Vernier TDC的量化噪声
▸GRO操作实现一阶噪声整形
Abstract
Two gated ring oscillators (GROs) act as the delay
lines in an improved V ernier time -to-digital converter (TDC),
where the already small quantization noise of the standard Vernier
TDC is further first-order shaped by the GRO operation. The TDC
has been implemented in a 90 nm CMOS process and consumes
3 mA from 1.2 V when operating at 25 MHz. The native Vernier
resolution of the TDC is 5.8 ps, while the total noise integrated
over a bandwidth of 800 kHz yields an equivalent TDC resolution
of 3.2