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A 65 nm 850 MHz 256 kbit 43 pJaccess Ultra Low Leakage Power Memory Using Dynami
本文设计了一种高速超低功耗SRAM存储器，采用分位线和局部写感放大器等技术，显著降低功耗并提升性能。
65nm CMOS, 850MHz, 4.3pJ/access, 25.2μW standby leakage
SRAM低功耗高速分位线局部写感放大器
▸分位线设计提高动态单元稳定性并降低能耗
▸局部写感放大器实现全局位线低摆幅信号
▸使用高阈值晶体管减少静态功耗并提升读取稳定性
Abstract
This paper presents the design of a high-speed ultra
low power SRAM memory. Divided bit lines improve dynamic cell
stability while at the same time dec reasing active energy consump-
tion. To limit unnecessary activ ity, word lines are divided on a
word-by-word basis. Local write sense ampli fiers make it possible
to use low swing signaling on the global bit lines. To control this
architecture, a distributed decoder is used. The use of dual swing
data links on the global bit lines limits the impa