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An Embedded Dynamic V oltage Scaling (DVS) System Through 55 nm Single-Inductor Dual-Output (SIDO) Switching Converter for 12-Bit Video Digital-to-Analog Converter Wen-Shen Chou, Tzu-Chi Huang , Student Member , IEEE,Y u - H u e i L e e, Student Member , IEEE, Y ao-Yi Y ang, Student Member , IEEE, Yi-Ping Su
55nm CMOS工艺下集成动态电压调节系统的12位电流导向视频DAC,提升能效。
55nm CMOS, 1V输出摆幅, 1MHz输入, 69.88dB SFDR
动态电压调节单电感双输出数字模拟转换器能效优化视频DAC
▸创新点1:双DVS控制降低功耗(系统创新) - 提出数字和模拟电路的双动态电压缩放(DVS)控制方法,通过动态调整供电电压,显著降低系统功耗,在DVS和PO模式下分别提升能效11.5%和28%。
▸创新点2:3S方法改善DNL/INL性能(方法创新) - 采用手指分离、分割和移位(3S)技术优化电流源布局,无需额外校准即可实现0.78/0.4 LSB的DNL和1.3/1.0 LSB的INL性能,同时抑制SIDO转换器的开关噪声干扰。
▸创新点3:改进SIDO转换器交叉调节性能(电路创新) - 通过优化SIDO转换器设计,大幅提升瞬态和稳态下的交叉调节性能,减少对模拟电源的干扰,确保DAC在1V输出摆幅和1MHz输入下实现69.88 dB的SFDR。
▸创新点4:集成SIDO供电的DAC系统(系统创新) - 将12位电流导向视频DAC直接由SIDO转换器供电,形成紧凑的DVS系统,兼具面积和能效优势,支持高清视频DAC性能。
Abstract
This paper proposes a 55 nm CMOS 12-bit cur- rent-steering video digital-to-analog converter (DAC) directly powered by the single-inductor dual-output (SIDO) switching converter to compose a dynamic voltage scaling (DVS) system and improve the power ef ficiency. Dual-DVS control in both digital and analog circuits can effectively reduce power consumption. With various supply voltages, the video DAC can meet several different speci fications in the power optimized (PO) mode. Fur- thermore, for DAC, the proposed 3S method, including finger separating, splitting and shifting, achieves good differential non- linearity (DNL) performance to 0.78/0.4 least signi ficant bit (LSB) and integral nonlinearity (INL) 1.3/1.0 LSB (with/without SIDO converter) without additional calibration. It also suppresses the switching noise interference from the SIDO converter. Moreover, for SIDO converter, the cross-regulation performance is greatly improved in both transient and steady state to achieve lowest interference for the analog supply. The total power ef ficiency can be improved up to 11.5% and 28% in the DVS and the PO mode. The SIDO supplied DAC with the dual-DVS function achieves 69.88 dB spurious free dynamic range (SFDR) at the 1 V output swing and 1 MHz input. The proposed intrinsic 12-bit DAC and SIDO converter achieve high de finition video DAC performance with the bene fit of area and energy ef ficiency.