← 返回 JSSC 论文列表JSSC 2012第8期RF & Wireless65nmHigh-Speed Link
016-025 pJbit 8 Gbs Near-Threshold Serial Link Receiver With Super-Harmonic Inje
提出一种近阈值电压的串行链路接收器，采用0.6V供电和超级谐波注入锁定技术实现低功耗。
65nm CMOS, 0.6V/1V, 8Gb/s, 0.163pJ/bit（无S/H）和0.25pJ/bit（带S/H）
近阈值电压串行链路接收器超级谐波注入锁定低功耗高并行度
▸创新点1：近阈值电压操作（0.6V供电）——采用近阈值电压设计技术，将大部分电路工作在0.6V低电压下，显著降低功耗，仅全局时钟缓冲器、测试缓冲器和数字电路工作在标准1V电压，实现了0.163 pJ/bit的超低能耗指标。
▸创新点2：超级谐波注入锁定环形振荡器——提出一种新型低功耗超级谐波注入锁定环形振荡器，用于生成可去偏斜的对称多相本地时钟相位，解决了低电压下时钟同步的难题，提升了系统稳定性。
▸创新点3：高并行度1:10解复用设计——通过1:10的高并行度解复用架构，在低电压下确保量化器正常工作，实现了8 Gb/s的高数据速率，同时维持了低功耗特性。
▸创新点4：采样保持电路优化——通过在不同原型中集成采样保持（S/H）电路，验证了其在低电压下改善量化器孔径时间的性能影响，最终实现了0.25 pJ/bit的能效，并在20-cm FR4 PCB通道上达到BER<10^-12。
Abstract
A near-threshold forwarded-clock I/O receiver archi-
tecture is presented. In the proposed receiver, the majority of the
circuitry is designed to operate in the near-threshold region at 0.6 V
supply to save power, with the exception of only the global clock
buffer, test buffers and s ynthesized digital circuits at the nominal
1 V supply. To ensure the quantizers are working properly with this
low supply, a 1:10 direct demulti plexing rate is chosen as a demon-
stration of achieving low supply op