0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking

Abstract

A near-threshold forwarded-clock I/O receiver archi- tecture is presented. In the proposed receiver, the majority of the circuitry is designed to operate in the near-threshold region at 0.6 V supply to save power, with the exception of only the global clock buffer, test buffers and s ynthesized digital circuits at the nominal 1 V supply. To ensure the quantizers are working properly with this low supply, a 1:10 direct demulti plexing rate is chosen as a demon- stration of achieving low supply operation by high-parallelism. A novel low-power super-harmonic injection-locked ring oscillator is proposed to generate deskewab le symmetric multi-phase local clock phases. The relative perfor mance impact of including a per- data lane sample-and-hold (S/H) to improve quantizer aperture time at low voltage is demonstrated with two receiver prototypes fabricated in a 65 nm CMOS technology. Including the amortized power of global clock distribution, the receiver without S/H con- s u m e s1 . 3m Wa n dt h eo n ew i t hS / Hc o n s u m e s2m Wa ta n8G b / s input data rate, which converts to 0.163 pJ/bit and 0.25 pJ/bit, respectively. Measurement results show both receivers get BER 10 across a 20-cm FR4 PCB channel.