← 返回 JSSC 论文列表JSSC 2012第8期RF & Wireless45nm SOI CMOS
A 16-Gbs Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic A
一款用于多标准背板的16Gb/s收发器，采用12抽头DFE和动态适应技术
16 Gb/s, 30 dB损耗通道, 385 mW/link
收发器背板DFE动态适应16Gb/s
▸创新点1：12抽头DFE接收器采用电流积分技术，显著提高信号处理精度和速度，支持16Gb/s高速数据传输，适用于多标准背板应用。
▸创新点2：动态适应技术通过实时调整电路参数，有效应对电压和温度变化带来的参数漂移，确保系统稳定性和可靠性。
▸创新点3：3抽头FFE发射器结合源端串联终端驱动技术，优化信号完整性，支持超过30dB损耗通道的无误码NRZ信号传输。
▸创新点4：8端口核心设计集成双PLL，实现高效时钟管理，整体功耗低至385mW/link，兼顾高性能与低功耗需求。
Abstract
This paper presents a 16-Gb/s 45-nm SOI CMOS
transceiver for multi-standa rd backplane applications. The re-
ceiver uses a 12-tap DFE with circuit re finements for supporting
higher data rates. Both the receiver and the transmitter use
dynamic adaptation to co mbat parameter drift due to changing
supply voltage and temperature. A 3-tap FFE is included in the
source-series-terminated driver. The combination of DFE and
FFE permits error-fre e NRZ signaling at 16 Gb/s over channels
exceeding 30 dB l