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A 40-mW 7-bit 22-GSs Time-Interleaved Subranging CMOS ADC for Low-Power Gigabit
一款用于低功耗千兆位无线通信SoC的7位2.2GS/s时间交织子范围CMOS ADC
65nm CMOS, 1V, 2.2GS/s, 40mW, 0.3mm²
时间交织子范围ADC低功耗CMOS无线通信SoC
▸时间分割子范围架构提升ADC通道速度
▸低功耗快速稳定分布式电阻阵列减少增益失配
▸数字控制校正电流源校准通道偏移失配
Abstract
A 7-bit, 2.2-GS/s time-interleaved subranging CMOS
analog-to-digital converter (ADC) for low-power gigabit wireless
communication system-on-a-chip (SoC) is presented. A time-split-
ting subranging architecture is invented to signi ficantly boost the
speed of individual ADC channels . In addition, a low-power and
fast-settling distributed resistor array for reference voltages is pro-
posed to mitigate gain mismatches within channels. Moreover, the
channel offset mismatches are calibrated through t