JSSC 2012第9期Data Converters90nmPipeline ADC

A 12-b 30-MSs 295-mW Pipelined ADC Using Single-Stage Class-AB Ampli ﬁers and De

采用单级低增益AB类放大器和数字校准技术的12位30MS/s低功耗流水线ADC

90nm CMOS, 1.2V, 30MS/s, 295mW, 64.5dB SNDR

流水线ADCAB类放大器数字校准低功耗设计多项式建模

▸使用单级低增益AB类放大器动态提供负载电流

▸采用电源循环技术仅在残余放大阶段开启放大器

▸基于分段三次多项式模型的数字背景校准方案

Abstract

A 12-b 30-MS/s pipelined ADC is realized using single-stage, low-gain, class-AB ampli ﬁers, which can dynamically provide the load currents without large static currents. In addi- tion, the ampli ﬁers are power cycled and turned on only during residue ampli ﬁcation to enable further power savings. Nonlinear errors due to ﬁnite gain are addressed using a deterministic digital background calibration scheme. The ampli ﬁer’s transfer func- tion is piecewise modeled in our calibration scheme using th