A 12-b, 30-MS/s, 2.95-mW Pipelined ADC Using Single-Stage Class-AB Ampli fiers and Deterministic Background Calibration Justin Kyung-Ryun Kim

Abstract

A 12-b 30-MS/s pipelined ADC is realized using single-stage, low-gain, class-AB ampli fiers, which can dynamically provide the load currents without large static currents. In addi- tion, the ampli fiers are power cycled and turned on only during residue ampli fication to enable further power savings. Nonlinear errors due to finite gain are addressed using a deterministic digital background calibration scheme. The ampli fier’s transfer func- tion is piecewise modeled in our calibration scheme using three third-order polynomial function s (splines) for low computational overhead. The presented ADC occupies an active area of 0.36 mm in 90-nm CMOS. It dissipates 2.95 mW from a 1.2-V supply and achieves an SNDR of 64.5 dB f or inputs near Nyquist. The corresponding figure of merit is 72 fJ/conversion-step.