A 20-b 40-mV Range Read-Out IC With 50-nV Offset and 0.04% Gain Error for

Abstract

This paper presents a 20-b read-out IC with 40-mV full-scale range that is intended for use with bridge transducers. It consists of a current-fee dback instrumentation ampli fier (CFIA) followed by a switched-capacitor incremental ADC. The CFIA’s offset and noise are mitigated by chopping, while its gain accuracy and gain d rift are improved by applying dynamic element matching to its input and feedback transconductors. Their mismatch is reduced by a digitally assisted correction loop, which further reduce s the CFIA’s gain drift. Finally, bulk-bi- asing and impedance-balancing techniques are used to reduce the common-mode dependency of these transconductors, which would otherwise limit the achievable gai n accuracy. The com- bination of these techniques enables the read-out IC to achieve 140-dB CMRR, a worst-case gain error of 0.04% over a 0–2.5 V common-mode r ange, a maximum gain drift of 0.7 ppm/ Ca n d an INL of 5 ppm. After applying nested-chopping, the read-out IC achieves 50-nV offset, 6-nV/ C offset drift, a thermal noise floor of 16.2 nV/ Hza n da0 . 1 - m H z noise corner. Implemented in a0 . 7 - m CMOS technology, the protot ype read-out IC consumes 270 Af r o ma5 - Vs u p p l y .