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A 579-Gbs Energy-Efficient Multirate LDPC Codec Chip for IEEE 802153c Application
一款支持IEEE 802.15.3c四种码率的高效能LDPC编解码芯片，采用65nm工艺，最高吞吐量5.79Gb/s。
65nm CMOS, 5.79Gb/s吞吐量, 3.7Gb/s/mm²硬件效率, 62.4pJ/b能效
LDPC编解码器IEEE 802.15.3c归一化最小和算法可重构排序器能效优化
▸基于行的分层调度减少迭代次数
▸可重构8/16/32输入排序器支持多码率
▸加法器-累加器-移位寄存器电路降低编码器复杂度
Abstract
An LDPC codec chip supporting four code rates
of IEEE 802.15.3c applications is presented. After utilizing
row-based layered scheduling, the normalized min-sum (NMS) al-
gorithm can reduce half of the iteration number while maintaining
similar performance. According to the unique code structure of
the parity-check matrix, a recon figurable 8/16/32-input sorter is
designed to deal with LDPC codes in four different code rates.
Both sorter input reallocation and pre-coded routing switch are
proposed