← 返回 JSSC 论文列表JSSC 2012第9期Other0.35 µm
A Fully Autonomous Integrated Interface Circuit for
一种全自主自适应脉冲同步电荷提取器电路,专为宽输出电压范围的压电能量收集器优化。
0.35 µm CMOS, 1.3–20 V, 85%效率
压电能量收集器自适应电路同步电荷提取低功耗能量转换效率
▸自适应脉冲同步电荷提取器(PSCE)
▸低功耗设计(最小5.7 µW)
▸改进的开关技术提高提取功率20%
Abstract
This paper presents a fully autonomous, adaptive pulsed synchronous charge extractor (PSCE) circuit optimized for piezoelectric harvesters (PEHs) which have a wide output voltage range 1.3–20 V. The PSCE chip fabricated in a 0.35 µm CMOS process is supplied exclusively by the buffer capacitor where the harvested energy is stored in. Due to the low power consumption, the chip can handle a minimum PEH output power of 5.7 µW. The system performs a startup from an uncharged buffer capacitor and operates in the adaptive mode at storage buffer voltages f r o m1 . 4Vt o5V .B yr e d u c i n gt h es e r i e sr e s i s t a n c el o s s e s ,t h e implementation of an improved switching technique increases the extracted power by up to 20% compared to the formerly presented Synchronous Electric Charge Extraction (SECE) technique and enables the chip efficiency to reach values of up to 85%. Compared to a low-voltage-drop passive full-wave recti fier, t he PSCE chip increases the extracted power to 123% when the PEH is driven at resonance and to 206% at off-resonance.