A Pipelined ADC With Metastability Error Rate 10 Errors/Sample

Abstract

A prototype 10-bit 80-MS/s pipelined analog-to-dig- ital converter (ADC) implemented in a 0.25- mC M O Sp r o c e s si s described. The prototype uses a c ombination of time-interleaved and lookahead operations to allow one clock period for com- parator regeneration, reducing the bit error rate (BER) due to comparator metastability by a factor between 10 and 10 .A l s o , the front-end samp le-and-hold amplifier (SHA) previously used to provide a 1/2 clock period of regeneration time for the first-stage comparators in a lookahead pipelined ADC is eliminated [1], [2], reducing the power consumption and the input-referred noise. The analog power dissipation is 72 mW from a 2.5-V supply. At a sampling rate of 80 MS/s, the prototype achieves a peak signal-to-noise-and-distortion ratio of 58.3 dB for an input fre- quency of 80 kHz. Also, for a comparator bias current of 100 A, extrapolations from measurements show that the BER is 10 errors/sample.