← 返回 JSSC 论文列表JSSC 2012第9期Data Converters0.25μm CMOSPipeline ADC
A Pipelined ADC With Metastability Error Rate 10 ErrorsSample
一款10位80MS/s流水线ADC，通过时间交织和前瞻操作降低比较器亚稳态误码率。
10-bit, 80MS/s, 58.3dB SNDR, 72mW@2.5V
流水线ADC亚稳态时间交织前瞻操作误码率
▸采用时间交织和前瞻操作技术降低比较器亚稳态误码率
▸消除前端采样保持放大器以降低功耗和噪声
▸优化比较器再生时间设计
Abstract
A prototype 10-bit 80-MS/s pipelined analog-to-dig-
ital converter (ADC) implemented in a 0.25- mC M O Sp r o c e s si s
described. The prototype uses a c ombination of time-interleaved
and lookahead operations to allow one clock period for com-
parator regeneration, reducing the bit error rate (BER) due to
comparator metastability by a factor between 10
and 10 .A l s o ,
the front-end samp le-and-hold amplifier (SHA) previously used to
provide a 1/2 clock period of regeneration time for the first