Design of High Ef ficiency Monolithic Power Amplifier With Envelope-Tracking and Transistor Resizing for Broadband Wireless Applications Yan L i, Student Member , IEEE

Abstract

This paper presents the design insights for the imple- mentation of a fully monolithic radio frequency (RF) power am- plifier (PA) using both envelope-tracking (ET) and transistor re- sizing techniques for long-term evolution (LTE ) applications. At the low output power region, some of the power cells in the PA can be disabled to further save power consumption, thus enhancing the efficiency from a traditional ET-PA. Our E T-PA system is first realized with a two-chip solution, consisting of a high voltage en- velope modulator fabricated in a 0.35 m Bipolar-CMOS-DMOS (BCD) technology, and a differential cascode PA in a 0.35 mS i G e BiCMOS technology. This two-chip solution of the ET-PA is to showcase the effective ef ficiency enhancement of using the tran- sistor resizing method. In the secon dd e s i g n ,aC M O Se n v e l o p e modulator is integrated with the cascode PA on the same die in the 0.35 m SiGe BiCMOS technology. So me insights are demon- strated regarding the optimiz ation of the envelope modulator spe- cific to our cascode PA for LTE broadband signals, where the finite bandwidth and the switching frequency of the envelope modulator are considered for achievin g the minimal error-vector magnitude (EVM) and spurious noise. The fully monolithic BiCMOS ET-PA reaches the maximum linear output power ( )o f2 4d B ma n d 23.4 dBm with overall powe r-added-efficiency (PAE) of 41% and 38% for the LTE 16QAM 5 MHz and 10 MHz signals at 1.9 GHz, respectively, without needing predi