Digitally Calibrated 768-kS/s 10-b Minimum-Size SAR ADC Array With Dithering Ruoyu Xu, Student Member , IEEE, Bing Liu , Student Member , IEEE, and Jie Y uan, Member , IEEE

Abstract

Array sensors require a high-performance analog-to- digital converter (ADC) array with small area and low power. Successive-approximation register (SAR) ADC has good potential for ADC array due to its simple analog circuit s. However, SAR ADCs with 10-b resolution and higher normally need a large capacitor array due to the stringent matching requirement. The large capacitor array also limits the ADC d ynamic performance. The capacitor mismatch has been c ompensated by analog calibra- tion techniques. In this work, a novel digital calibration method is developed for SAR ADC based on dither ing. With dithering, w e i g h t so fm o s ts i g n ificant bit (MSB) capacitors can be measured accurately so that very small capacitors can be used in the SAR ADC due to the relaxed matching re quirement. A modi fied bit-cy- cling procedure is developed t o avoid the code gaps caused by capacitor dithering. This calibra tion technique requires no analog calibration overhead and simp le digital decoders. The technique is implemented in an ADC array design including 256 SAR ADCs for a high-speed CMOS imaging sensor in a 0.18- mC M O S process. The 10-b SAR ADC is d esigned with the minimum ca- pacitor array size in the process. A single SAR ADC only occupies 15 m 710 m. Sampling at 768 kS/s, peak DNL and peak INL of the original ADCs ave raged across the array are 0.82 least sig- nificant bit (LSB) and 3.85 LSB, respectively. For a signal close to the Nyquist frequency, original ADCs have 7.96-