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Event-Driven GHz-Range Continuous-Time Digital Signal Processor With Activity-Dependent
提出了一种无时钟、连续时间GHz处理器，采用边缘数字信号编码处理ps级时间间隔的样本。
0.07 mm²面积，0.8–3.2 GHz信号范围，动态范围超过20 dB，功耗1.1至10 mW
GHz处理器连续时间数字信号处理异步滤波动态范围
▸时钟less连续时间处理器：采用无时钟设计，通过事件驱动机制实现GHz范围的连续时间信号处理，突破了传统同步数字电路的速度限制，支持15 ps的超窄时间间隔采样（方法创新）
▸并行数字延迟链：利用多路并行数字延迟链结构实现高速信号的时间对齐与处理，每路延迟链在等待新样本时功耗极低，显著提升了系统能效比（电路创新）
▸可编程电荷泵实现异步滤波：通过可编程电荷泵动态配置滤波参数，结合异步处理机制使系统功耗（1.1-10 mW）随输入信号活动自动调节，在0.8-3.2 GHz范围内实现20 dB动态范围（系统创新）
▸3-bit连续时间闪存ADC集成：将高速闪存ADC与数字处理器单片集成，在0.07 mm²面积内完成六抽头滤波处理，实现模拟/数字混合信号处理的微型化（集成创新）
Abstract
Presented is a clockless, continuous-time (CT) GHz processor that bypasses some of t he limitations of conventional digital and analog implementations. Per-edge digital signal en- coding is used for parallel processing of continuous-time samples with a temporal spacing as narrow as 15 ps, generated by a 3-b CT flash ADC. Parallel digital delay chains and programmable charge pumps realize the asynchronous filtering operation, each con- suming negligible power while aw aiting a new sample. A six-tap CT ADC and CT digital FIR processor system occupies 0.07 mm and achieves dynamic range of over 20 dB in the 0.8–3.2-GHz signal range. The system’s rate of operations automatically adapts to the signal, thus causing its power dissipation to vary in the range of 1.1 to 10 mW according to input activity.