A 15-Gb/s 0.5-mW/Gbps Two-Tap DFE Receiver With Far-End Crosstalk Cancellation Meisam Honarvar Nazari , Student Member , IEEE

Abstract

This paper presents a low-power receiver with t w o - t a pd e c i s i o nf e e d b a c ke q u a lization (DFE) and novel far-end crosstalk (FEXT) cancellation capability, implem e n t e di na4 5 - n m SOI CMOS process. The receiver employs a half-rate speculative DFE architecture to allow for the use of low-power front-end circuitry and CMOS clock buffers. In the pro posed architecture, a switched-capacitor sample-ho ld at the front-end is employed to perform DFE tap summation. This technique is generalized to implement taps of equalization. The r eceiver compensates the effect of crosstalk without making a decision on the received aggressor signal. Due to the low-power nature of the switched-ca- pacitor front-end, the crosstalk canc ellation is possible with only 33 W/Gbps/lane power overhead. The receiver was tested over channels with different levels of loss and coupling. The signaling rate with BER 10 was signi ficantly increased with the use of DFE and crosstalk cancellation scheme for highly coupled and lossy PCB traces. The DFE recei ver equalizes 15-Gb/s data over a channel with more than 14-dB loss while consuming about 7.5 mW from a 1.2-V supply. At lower data rates it equalizes channels with over 21-dB loss.