A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor Ki Chul Chun, Wei Zhang , Student Member , IEEE, Pulkit Jain, and Chris H. Kim ,S e n i o rM e m b e r ,I E E E

Abstract

A truly logic-compatible gain cell eDRAM macro with no boosted supplies is presented. A 2T1C gain cell implemented only with regular thin oxide devices consists of an asymmetric 2T cell and a coupling PMOS capacitor. The PMOS capaci tor ensures proper operation even without a b oosted supply by utilizing a ben- eficial coupling for read and a preferential boosting for write. A re- pair scheme based on a single-ended 7T SRAM has fe atures such as a local differential write and shared control with the main 2T1C array. A storage voltage monitor is proposed to track the reten- tion characteristics of a gain cell eDRAM under PVT variations and to adjust its refresh rate adaptively. A 128 kb eDRAM test chip implemented in a 65 nm Low-Power (LP) process operates at a random access frequency of 714 MHz wit h a static power dissi- pation of 161.8 µW per Mb for a 500 µs refresh rate at 1.1 V and 85°C.