A New Approach to Low-Power and Low-Latency Wake-Up Receiver System for Wireless Sensor Nodes Dae-Y oung Y oon, Chang-Jin Jeong, Justin Cartwrig ht, Ho-Y ong Kang, Seok-Kyun Han, Nae-Soo Kim

Abstract

A new wake-up receiver is p roposed to reduce energy consumption and latency through adoption of two diff erent data rates for the transmission of wake-up packets. To reduce the en- ergy consumption, the start frame bits (SFBs) of a wake-up packet are transmitted at a low data rate of 1 kbps, an d a bit-level duty cycle is employed for detection of SFBs. To reduce both energy con- sumption and latency, duty cycling is halted upon detection of the SFB sequence, and the rest of the wake-up pa cket is transmitted at a higher data rate of 200 kbps. The proposed wake-up receiver is designed and fabricated in a 0.18 µm CMOS technology with a core size of 1 850x1560 µm for the target frequency range of 902–928 MHz. The measured results show that the proposed design achieves a sensitivity of 73 dBm, while dissipating an average power of 8.5 µW from a 1.8 V supply.