A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS Tao Jiang,S t u d e n tM e m b e r ,I E E E, Wing Liu, Freeman Y . Zhong, Charlie Zhong

Abstract

A single-channel, asynch ronous successive-approx- imation (SA) ADC with improved feedback delay is fabricated in 40 nm CMOS. Compared with a conventional SAR structure that employs a single quantiz er controlled by a digital feedback logic loop, the proposed SAR-ADC employs multiple quantizers for each conversion bit, clocked by an asynchronous ripple clock that is generated after eac h quantization. He nce, the sampling rate of the 6-bit ADC is limited only by the six delays of the Ca- pacitive-DAC settling and each comparator’s quantization delay, as the digital logic de lay is eliminated. Measurement results of the 40 nm-CMOS SAR-ADC achieves a peak SNDR of 32.9 dB and 30.5 dB, at 1 GS/s and 1.25 GS/s, consuming 5.28 mW and 6.08 mW, leading to a FoM o f 148 fJ/conv-step and 178 fJ/conv-step, respectively, in a core area less than 170 um by 85 um.