← 返回 JSSC 论文列表JSSC 2012第10期Data Converters40nmSAR ADC
A Single-Channel 125-GSs 6-bit 608-mW Asynchronous Successive-Approximation ADC
40纳米CMOS工艺下单通道异步逐次逼近ADC，实现1.25GS/s采样率与低功耗
6-bit 1.25GS/s 6.08mW 178fJ/conv-step
异步SAR ADC多量化器高速低功耗电容DAC比较器延迟优化
▸采用多量化器结构替代传统单量化器
▸异步纹波时钟消除数字逻辑延迟
▸电容DAC建立时间与比较器量化延迟决定采样速率
Abstract
A single-channel, asynch ronous successive-approx-
imation (SA) ADC with improved feedback delay is fabricated
in 40 nm CMOS. Compared with a conventional SAR structure
that employs a single quantiz er controlled by a digital feedback
logic loop, the proposed SAR-ADC employs multiple quantizers
for each conversion bit, clocked by an asynchronous ripple clock
that is generated after eac h quantization. He nce, the sampling
rate of the 6-bit ADC is limited only by the six delays of the Ca-
pacitiv