2.4 Gbps, 7 mW All-Digital PVT-V ariation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors Sanu K. Mathew , Member , IEEE

Abstract

This paper describes an all-digital PV T-variation tolerant true-random number generator (TRNG), fabricated in 45 nm high-k/metal-gate CMOS, targeted for on-die entropy generation in high-performance microprocess ors. The TRNG harvests differential thermal-noise at the diffusion nodes of a pre-charged cross-coupled inverter pair to resolve out of metasta- bility, generating one random bit/cycl e. A self-calibrating 2-step tuning mechanism using coarse-grained con figurable inverters and fine-grained programmable clock delay generators, along with an entropy-tracking feedback loop pr ovide tolerance to 20% PVT variation-induced device mismat ches, enabling lowest-reported energy-consumption of 2.9 pJ/bit with a dense layout occupying 4004 µm , while achieving: (i) 2.4 Gb ps random bit throughput, 7 mW total power consumption with 0.7 mW leakage power component, measured at 1.1 V , 50 C, (ii) random bitstreams that passes all NIST RNG tests with raw entropy/bit measured up to 0.9999999993, (iii) good distribution of 1’s with 4-bit entropy of 3.97996 and high-entropy pattern probability of 0.066 (iv) wide operating supply voltage ra nge with robust sub-threshold voltage performance of 14 Mbps, 5. 6 µW, measured at 280 mV , 50 C, (v) 12 fine-grained high-entropy settings for the TRNG to dither in during steady-state op eration, (vi) 3% error while using an analytical ergodic Markov chai n model for predicting pattern probabilities and (vii) 200x higher throughput and 9x higher en- e