A 10-b Ternary SAR ADC With Quantization Time Information Utilization Jon Guerber, Student Member , IEEE , Hariprasath V enkatram , Student Member , IEEE

Abstract

The design of a ternary successive approximation (TSAR) analog-to-digital converter (ADC) with quantization time information utilization is proposed. The TSAR examines the tran- sient information of a typical dynamic SAR voltage comparator to provide accuracy, speed, and power bene fits. Full half-bit redundancy is shown, allowing for residue shaping which provides an additional 6 dB of signal-to-quantization-noise ratio (SQNR). Synchronous quantizer speed enhancements allow for a shorter worst case conversion time. An increased monotonicity switching algorithm, stage skipping due to reference grouping, and SAR logic modi fications minimize overall dynamic energy. The archi- tecture has been shown to reduce capacitor array switching power consumption and digital-to-analog converter (DAC) driver power by about 60% in a mismatch limited SAR, reduce comparator activity by about 20%, and require only 8.03 average comparisons and 6.53 average DAC movements for a 10-b ADC output word. A prototype is fabricated in 0.13- m CMOS employing on-chip statistical time reference calibration, supply variability from 0.8 to 1.2 V , and small input signal po w e rs c a l i n g .T h ec h i pc o n s u m e s 84 W at 8 MHz with an effective number of bits of 9.3 for a figure of merit of 16.9 fJ/C-S for the 10-b prototype and 10.0 fJ/C-S for a 12-b enhanced prototype chip.